The present invention relates to a semiconductor integrated circuit device, and more particularly to techniques which are effective when applied to a semiconductor integrated circuit device having bipolar transistors.
More concretely, the present invention relates to a semiconductor integrated circuit device having a bipolar memory. In particular, it relates to techniques which are effective when applied to a bipolar-static random access memory (hereinbelow, abbreviated to "SRAM") which includes a Schottky barrier diode element and a resistance element connected in series with the cathode region of the diode element.
A semiconductor integrated circuit device, such as memory LSI or logic LSI, constructed mainly of bipolar transistors tends to be heightened in the density of integration. A bipolar transistor which the inventors are developing adopts a side wall base contact structure (hereinbelow, termed "SICOS") as described in, for example, Japanese Patent Application No. 225738/1984.
The SICOS-bipolar transistor is such that a base region is constructed in a salient (convex) island region of silicon which is formed in an active region, and that a base lead-cut electrode is connected to the base region at the side wall of the salient island region. Thus, the SICOS-bipolar transistor has the feature that the occupation area of the base region is reduced in correspondence with the contact area between the base region and the base lead-out electrode, so a higher density of integration can be attained.
In the semiconductor integrated circuit device having the memory LSI, there are employed a forward bipolar transistor which utilizes a transistor action in the forward direction of the SICOS and a reverse bipolar transistor which utilizes a transistor action in the reverse direction of the SICOS (noting that in this specification the term "reverse" transistor will be used to have an identical meaning to the term "inverse transistor" which is frequently used in this art).
The forward bipolar transistor is constructed of a vertical structure in which an emitter region, a base region and a collector region are provided in the direction of the depth of a semiconductor substrate successively from the front surface side of a salient island region formed of an epitaxial layer of single-crystal silicon grown on the principal surface of the semiconductor substrate. The emitter region is constructed of an n-type semiconductor region of high impurity concentration. The base region is constructed of a p-type semiconductor region. The collector region is constructed of an n-type epitaxial layer of low impurity concentration which is provided on a side lying in contact with the base region, and a buried n-type semiconductor region of high impurity concentration which is provided under the n-type epitaxial layer. Such bipolar transistors are used in a peripheral circuit and a logic portion except a resistance switching type memory cell with Schottky barrier diodes (hereinbelow, abbreviated to "SBDs") which the inventors are developing. Since the forward bipolar transistor holds the lightly-doped part (the epitaxial layer) of the collector region in contact with the base region, it has the feature that a p-n junction capacitance which is formed between the base region and the collector region can be lowered, so the operating speed of this transistor can be raised.
The reverse bipolar transistor is constructed of a vertical structure in which a collector region, a base region and an emitter region are provided in the direction of the depth of a salient island region successively from the front surface side thereof. The collector region is constructed of an n-type semiconductor region of high impurity concentration. The base region is constructed of a p-type semiconductor region. The emitter region is constructed of an n-type epitaxial layer of low impurity concentration which is provided on a side lying in contact with the base region, and a buried n-type semiconductor region of high impurity concentration which is provided under the n-type epitaxial layer. Such reverse bipolar transistors constitute the resistance switching type memory cell with SBDs. The reverse bipolar transistor is such that the collector region to serve as the charge storage portion (storage node portion) of the memory cell is constructed on the front surface side of the substrate through the base region. Thus, the reverse bipolar transistor has the feature that the influence of minority carriers created by the entrance of alpha particles into the substrate can be relieved to enhance the soft-error immunity of the transistor against the alpha particles.
The SICOS is a peculiar structure in which the respective operating regions are defined into the vertical structure by the salient island region of silicon. The reverse bipolar transistor is constructed of the simple structure in which the collector region and emitter region of the forward bipolar transistor are replaced with each other. In addition, the respective operating regions of the reverse bipolar transistor are formed by the same manufacturing steps as those of the respective operating regions of the forward bipolar transistor. More specifically, the collector region, base region and emitter region of the reverse bipolar transistor are respectively formed by the same manufacturing steps and at the same impurity concentration distributions as those of the emitter region, base region and collector region of the forward bipolar transistor. The semiconductor integrated circuit device thus constructed has the feature that the number of manufacturing steps can be reduced.
Besides, a bipolar memory to be carried in a semiconductor integrated circuit device which the inventors are developing is an SRAM. Each memory cell in the bipolar memory is constructed of the resistance switching type memory cell with SBDs. This memory cell is configured mainly of the forward bipolar transistors, the reverse bipolar transistors, the SBD elements, low resistance elements and high resistance elements.
Each of the forward bipolar transistor and the reverse bipolar transistor is constructed of the SICOS.
The SBD element is constructed of a cathode region which is formed of an n-type semiconductor region, and a metal film which is held in contact with the front surface of the n-type semiconductor region being the cathode region. The metal film used is, for example, a platinum silicide film.
The low resistance element is constructed of an n-type semiconductor region which is formed to be unitary with the cathode region of the SBD element. The n-type semiconductor region constructing the low resistance element, and the n-type semiconductor region constituting the SBD element are formed in such a way that, at one manufacturing step, an n-type impurity is introduced into the principal surface part of the semiconductor substrate by ion implantation and is subjected to drive-in diffusion. Thus, the low resistance element and the cathode region of the SBD element are formed by the identical manufacturing step, to bring forth the feature that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced.
The high resistance element is constructed of a p-type semiconductor region or an n-type semiconductor region.